AD9925 |
RFQ for AD9925 Required Field |
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| Technical/Catalog Information | AD9925BBCZ |
| Vendor | Analog Devices Inc |
| Category | Integrated Circuits (ICs) |
| Package / Case | 96-CSPBGA |
| Packaging | Tape & Reel (TR) |
| Type | CCD Signal Processor |
| Interface | 3-Wire Serial |
| Supply Voltage | 2.7 V ~ 3.6 V |
| Current - Supply | - |
| Input Type | Logic |
| Output Type | Logic |
| Lead Free Status | Lead Free |
| RoHS Status | RoHS Compliant |
| Other Names | AD9925BBCZ AD9925BBCZ |
| Product | Manufacturers | Pack | D/C |
| AD9925 | - | new | - |
The AD9925 is a complete 36 MHz front end solution for digi-tal still camera and other CCD imaging applications. Based on the AD9995 product, the AD9925 includes the analog front end and a fully programmable timing generator (AFETG), combined with a 10-channel vertical driver (V-driver). A Precision Timing core allows adjustment of high speed clocks with approximately 600 ps resolution at 36 MHz operation.
The on-chip V-driver supports up to 10 channels for use with 3-field (6-phase) CCDs. Two additional vertical outputs can be used with CCDs that contain advanced video readout modes. Voltage levels of up to +15 V and −8 V are supported.
The analog front end includes black level clamping, CDS, VGA, and a 12-bit ADC. The timing generator and V-driver provide all the necessary CCD clocks: RG, H-clocks, vertical clocks, sensor gate pulses, substrate clock, and substrate bias control. The internal registers are programmed using a 3-wire serial interface.
Packaged in an 8 mm × 8 mm CSPBGA, the AD9925 is speci-fied over an operating temperature range of −25°C to +85°C.
Typical Application |
Features |
| Digital still camerasDigital video camcordersCCD camera modules | Integrated 10-channel V-driverRegister-compatible with the AD9991 and AD99953-field (6-phase) vertical clock support2 additional vertical outputs for advanced CCDsComplete on-chip timing generatorPrecision Timing core with <600 ps resolutionCorrelated double sampler (CDS)6 dB to 42 dB 10-bit variable gain amplifier (VGA)12-bit 36 MHz ADCBlack level clamp with variable level controlOn-chip 3 V horizontal and RG drivers2-phase and 4-phase H-clock modesElectronic and mechanical shutter supportOn-chip driver for external crystalOn-chip sync generator with external sync input8 mm × 8 mm CSPBGA package with 0.65 mm pitch |
| Parameter | With Respect To | Min | Max | Unit |
| VDD | VDVSS | VDVSS − 0.3 | VDVSS + 4 | V |
| VL | VDVSS | VDVSS − 10.0 | VDVSS + 0.3 | V |
| VH1, VH2 | VDVSS | VL 0.3 | VL + 27.0 | V |
| VM1, VM2 | VDVSS | VL 0.3 | VL + 27.0 | V |
| AVDD | AVSS | −0.3 | +3.9 | V |
| TCVDD | TCVSS | −0.3 | +3.9 | V |
| HVDD | HVSS | −0.3 | +3.9 | V |
| RGVDD | RGVSS | −0.3 | +3.9 | V |
| DVDD | DVSS | −0.3 | +3.9 | V |
| DRVDD | DRVSS | −0.3 | +3.9 | V |
| RG Output | RGVSS | −0.3 | RGVDD + 0.3 | V |
| H1 to H2 Output | HVSS | −0.3 | HVDD + 0.3 | V |
| Digital Outputs | DVSS | −0.3 | DVDD + 0.3 | V |
| Digital Inputs | DVSS | −0.3 | DVDD + 0.3 | V |
| SCK, SL, SDATA | DVSS | −0.3 | DVDD + 0.3 | V |
| REFT/REFB, CCDIN | AVSS | −0.3 | AVDD + 0.3 | V |
| Junction Tempera-ture | 150 | °C | ||
| Lead Temperature, 10 s | 350 | °C |
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